-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 5.0 Build 148 04/26/2005 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY UnidadeProcessamento IS 
	port
	(
		PCWriteCond :  IN  STD_LOGIC;
		PCWrite :  IN  STD_LOGIC;
		IorD :  IN  STD_LOGIC;
		MemWrite :  IN  STD_LOGIC;
		IRWrite :  IN  STD_LOGIC;
		usaSinal :  IN  STD_LOGIC;
		RegBWrite :  IN  STD_LOGIC;
		BEQorBNE :  IN  STD_LOGIC;
		RegWrite :  IN  STD_LOGIC;
		reset :  IN  STD_LOGIC;
		clk :  IN  STD_LOGIC;
		RegMDR :  IN  STD_LOGIC;
		countControl :  IN  STD_LOGIC;
		causeWrite :  IN  STD_LOGIC;
		HILO :  IN  STD_LOGIC;
		ALUOutWrite :  IN  STD_LOGIC;
		EPCWrite :  IN  STD_LOGIC;
		causeSrc :  IN  STD_LOGIC;
		excecao_to_PC :  IN  STD_LOGIC;
		MultControl :  IN  STD_LOGIC;
		AluOp :  IN  STD_LOGIC_VECTOR(2 downto 0);
		AluSrcA :  IN  STD_LOGIC_VECTOR(1 downto 0);
		AluSrcB :  IN  STD_LOGIC_VECTOR(1 downto 0);
		DataToReg :  IN  STD_LOGIC_VECTOR(2 downto 0);
		PCSource :  IN  STD_LOGIC_VECTOR(1 downto 0);
		RegAControl :  IN  STD_LOGIC_VECTOR(1 downto 0);
		RegDst :  IN  STD_LOGIC_VECTOR(1 downto 0);
		WoHoB :  IN  STD_LOGIC_VECTOR(1 downto 0);
		
		LTControl : IN STD_LOGIC;
		
		overflowALU :  OUT  STD_LOGIC;
		FinishMultControl :  OUT  STD_LOGIC;
		funct :  OUT  STD_LOGIC_VECTOR(5 downto 0);
		opcode :  OUT  STD_LOGIC_VECTOR(5 downto 0)
	);
END UnidadeProcessamento;

ARCHITECTURE bdf_type OF UnidadeProcessamento IS 

component ula32
	PORT(A : IN STD_LOGIC_VECTOR(31 downto 0);
		 B : IN STD_LOGIC_VECTOR(31 downto 0);
		 Seletor : IN STD_LOGIC_VECTOR(2 downto 0);
		 Overflow : OUT STD_LOGIC;
		 Negativo : OUT STD_LOGIC;
		 z : OUT STD_LOGIC;
		 Igual : OUT STD_LOGIC;
		 Maior : OUT STD_LOGIC;
		 Menor : OUT STD_LOGIC;
		 S : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component registrador
	PORT(Clk : IN STD_LOGIC;
		 Reset : IN STD_LOGIC;
		 Load : IN STD_LOGIC;
		 Entrada : IN STD_LOGIC_VECTOR(31 downto 0);
		 Saida : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component banco_reg
	PORT(Clk : IN STD_LOGIC;
		 Reset : IN STD_LOGIC;
		 RegWrite : IN STD_LOGIC;
		 ReadReg1 : IN STD_LOGIC_VECTOR(4 downto 0);
		 ReadReg2 : IN STD_LOGIC_VECTOR(4 downto 0);
		 WriteData : IN STD_LOGIC_VECTOR(31 downto 0);
		 WriteReg : IN STD_LOGIC_VECTOR(4 downto 0);
		 ReadData1 : OUT STD_LOGIC_VECTOR(31 downto 0);
		 ReadData2 : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component extensor1_32
	PORT(entrada : IN STD_LOGIC;
		 saida : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component mux2
	PORT(seletor : IN STD_LOGIC;
		 entrada0 : IN STD_LOGIC_VECTOR(31 downto 0);
		 entrada1 : IN STD_LOGIC_VECTOR(31 downto 0);
		 saida : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component extensorsemsinal
	PORT(entrada : IN STD_LOGIC_VECTOR(15 downto 0);
		 saida : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component extensorsinal
	PORT(entrada : IN STD_LOGIC_VECTOR(15 downto 0);
		 saida : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component instr_reg
	PORT(Clk : IN STD_LOGIC;
		 Reset : IN STD_LOGIC;
		 Load_ir : IN STD_LOGIC;
		 Entrada : IN STD_LOGIC_VECTOR(31 downto 0);
		 Instr15_0 : OUT STD_LOGIC_VECTOR(15 downto 0);
		 Instr20_16 : OUT STD_LOGIC_VECTOR(4 downto 0);
		 Instr25_21 : OUT STD_LOGIC_VECTOR(4 downto 0);
		 Instr31_26 : OUT STD_LOGIC_VECTOR(5 downto 0)
	);
end component;

component loads
	PORT(entrada : IN STD_LOGIC_VECTOR(31 downto 0);
		 seletor : IN STD_LOGIC_VECTOR(1 downto 0);
		 saida : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component luibox
	PORT(entrada : IN STD_LOGIC_VECTOR(15 downto 0);
		 saida : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component memoria
	PORT(Clock : IN STD_LOGIC;
		 Wr : IN STD_LOGIC;
		 Address : IN STD_LOGIC_VECTOR(31 downto 0);
		 Datain : IN STD_LOGIC_VECTOR(31 downto 0);
		 Dataout : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component multiplicador
	PORT(multControl : IN STD_LOGIC;
		 clk : IN STD_LOGIC;
		 reset : IN STD_LOGIC;
		 multiplicador : IN STD_LOGIC_VECTOR(31 downto 0);
		 multiplicando : IN STD_LOGIC_VECTOR(31 downto 0);
		 finishMultControl : OUT STD_LOGIC;
		 saidaHI : OUT STD_LOGIC_VECTOR(31 downto 0);
		 saidaLO : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component mux2_5
	PORT(seletor : IN STD_LOGIC;
		 entrada0 : IN STD_LOGIC_VECTOR(4 downto 0);
		 entrada1 : IN STD_LOGIC_VECTOR(4 downto 0);
		 saida : OUT STD_LOGIC_VECTOR(4 downto 0)
	);
end component;

component mux4_5bits
	PORT(entrada0 : IN STD_LOGIC_VECTOR(4 downto 0);
		 entrada1 : IN STD_LOGIC_VECTOR(4 downto 0);
		 entrada2 : IN STD_LOGIC_VECTOR(4 downto 0);
		 entrada3 : IN STD_LOGIC_VECTOR(4 downto 0);
		 seletor : IN STD_LOGIC_VECTOR(1 downto 0);
		 saida : OUT STD_LOGIC_VECTOR(4 downto 0)
	);
end component;

component mux8
	PORT(entrada0 : IN STD_LOGIC_VECTOR(31 downto 0);
		 entrada1 : IN STD_LOGIC_VECTOR(31 downto 0);
		 entrada2 : IN STD_LOGIC_VECTOR(31 downto 0);
		 entrada3 : IN STD_LOGIC_VECTOR(31 downto 0);
		 entrada4 : IN STD_LOGIC_VECTOR(31 downto 0);
		 entrada5 : IN STD_LOGIC_VECTOR(31 downto 0);
		 entrada6 : IN STD_LOGIC_VECTOR(31 downto 0);
		 entrada7 : IN STD_LOGIC_VECTOR(31 downto 0);
		 seletor : IN STD_LOGIC_VECTOR(2 downto 0);
		 saida : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component mux3
	PORT(entrada0 : IN STD_LOGIC_VECTOR(31 downto 0);
		 entrada1 : IN STD_LOGIC_VECTOR(31 downto 0);
		 entrada2 : IN STD_LOGIC_VECTOR(31 downto 0);
		 seletor : IN STD_LOGIC_VECTOR(1 downto 0);
		 saida : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component mux4
	PORT(entrada0 : IN STD_LOGIC_VECTOR(31 downto 0);
		 entrada1 : IN STD_LOGIC_VECTOR(31 downto 0);
		 entrada2 : IN STD_LOGIC_VECTOR(31 downto 0);
		 entrada3 : IN STD_LOGIC_VECTOR(31 downto 0);
		 seletor : IN STD_LOGIC_VECTOR(1 downto 0);
		 saida : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component mux1b
	PORT(entrada0 : IN STD_LOGIC;
		 entrada1 : IN STD_LOGIC;
		 seletor : IN STD_LOGIC;
		 saida : OUT STD_LOGIC
	);
end component;

component shifterregister
	PORT(Clk : IN STD_LOGIC;
		 Reset : IN STD_LOGIC;
		 Entrada : IN STD_LOGIC_VECTOR(31 downto 0);
		 N : IN STD_LOGIC_VECTOR(4 downto 0);
		 Shift : IN STD_LOGIC_VECTOR(1 downto 0);
		 Saida : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component shiftleft2
	PORT(entrada : IN STD_LOGIC_VECTOR(31 downto 0);
		 saida : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component shiftleft2_26b
	PORT(entrada0 : IN STD_LOGIC_VECTOR(25 downto 0);
		entrada1 : IN STD_LOGIC_VECTOR(3 downto 0);
		 saida : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component masksave
	PORT(entradaMem : IN STD_LOGIC_VECTOR(31 downto 0);
		 entradaReg : IN STD_LOGIC_VECTOR(31 downto 0);
		 seletor : IN STD_LOGIC_VECTOR(1 downto 0);
		 saida : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

signal	AdressMem :  STD_LOGIC_VECTOR(31 downto 0);
signal	andPCWriteCond :  STD_LOGIC;
signal	causaExcecaoUm :  STD_LOGIC_VECTOR(31 downto 0);
signal	causaExcecaoZero :  STD_LOGIC_VECTOR(31 downto 0);
signal	causeException :  STD_LOGIC_VECTOR(31 downto 0);
signal	countToRegA :  STD_LOGIC_VECTOR(4 downto 0);
signal	entradaCauseException :  STD_LOGIC_VECTOR(31 downto 0);
signal	entradaNula :  STD_LOGIC_VECTOR(31 downto 0);
signal	entradaPC :  STD_LOGIC_VECTOR(31 downto 0);
signal	entradaRegA :  STD_LOGIC_VECTOR(31 downto 0);
signal	entradaRegB :  STD_LOGIC_VECTOR(31 downto 0);
signal	entradaWriteData :  STD_LOGIC_VECTOR(31 downto 0);
signal	entradaWriteReg :  STD_LOGIC_VECTOR(4 downto 0);
signal	entradaZero :  STD_LOGIC_VECTOR(31 downto 0);
signal	extendComSinal16_32 :  STD_LOGIC_VECTOR(31 downto 0);
signal	extendSemSinal16_32 :  STD_LOGIC_VECTOR(31 downto 0);
signal	flagSLTALU :  STD_LOGIC;
signal	flagZeroALU :  STD_LOGIC;
signal	instrucao :  STD_LOGIC_VECTOR(31 downto 0);
signal	loadPC :  STD_LOGIC;
signal	MDRtoLoads :  STD_LOGIC_VECTOR(31 downto 0);
signal	LuitoWriteData :  STD_LOGIC_VECTOR(31 downto 0);
signal	MDRtoWriteData :  STD_LOGIC_VECTOR(31 downto 0);
signal	multHI :  STD_LOGIC_VECTOR(31 downto 0);
signal	multLO :  STD_LOGIC_VECTOR(31 downto 0);
signal	Mux_causeToMuxALUOutPC :  STD_LOGIC_VECTOR(31 downto 0);
signal	notFlagZeroALU :  STD_LOGIC;
signal	Reg29 :  STD_LOGIC_VECTOR(4 downto 0);
signal	Reg31 :  STD_LOGIC_VECTOR(4 downto 0);
signal	resulSLTALU :  STD_LOGIC_VECTOR(31 downto 0);
signal	saida_MUX_BEQorNE :  STD_LOGIC;
signal	saida_Mux_RegAtoUla32 :  STD_LOGIC_VECTOR(31 downto 0);
signal	saida_Mux_RegBUla32 :  STD_LOGIC_VECTOR(31 downto 0);
signal	saidaALU :  STD_LOGIC_VECTOR(31 downto 0);
signal	saidaEPC :  STD_LOGIC_VECTOR(31 downto 0);
signal	saidaHILO :  STD_LOGIC_VECTOR(31 downto 0);
signal	saidaMux_sltToALUOut :  STD_LOGIC_VECTOR(31 downto 0);
signal	saidaMuxEntradaPC :  STD_LOGIC_VECTOR(31 downto 0);
signal	sel_ALUop :  STD_LOGIC_VECTOR(2 downto 0);
signal	sel_ALUOutWrite :  STD_LOGIC;
signal	sel_ALUSrcA :  STD_LOGIC_VECTOR(1 downto 0);
signal	sel_ALUSrcB :  STD_LOGIC_VECTOR(1 downto 0);
signal	sel_BEQorBNE :  STD_LOGIC;
signal	sel_causeSrc :  STD_LOGIC;
signal	sel_causeWrite :  STD_LOGIC;
signal	sel_clk :  STD_LOGIC;
signal	sel_countControl :  STD_LOGIC;
signal	sel_DataToReg :  STD_LOGIC_VECTOR(2 downto 0);
signal	sel_EPCWrite :  STD_LOGIC;
signal	sel_finishMultControl :  STD_LOGIC;
signal	sel_HILO :  STD_LOGIC;
signal	sel_IorD :  STD_LOGIC;
signal	sel_IRwrite :  STD_LOGIC;
signal	sel_MemWrite :  STD_LOGIC;
signal	sel_MultControl :  STD_LOGIC;
signal	sel_overflowALU :  STD_LOGIC;
signal	sel_PCSorce :  STD_LOGIC_VECTOR(1 downto 0);
signal	sel_PCwrite :  STD_LOGIC;
signal	sel_PCwriteCond :  STD_LOGIC;
signal	sel_RegAControl :  STD_LOGIC_VECTOR(1 downto 0);
signal	sel_RegBWrite :  STD_LOGIC;
signal	sel_RegDst :  STD_LOGIC_VECTOR(1 downto 0);
signal	sel_RegMDR :  STD_LOGIC;
signal	sel_RegWrite :  STD_LOGIC;
signal	sel_reset :  STD_LOGIC;
signal	sel_usaSinal :  STD_LOGIC;
signal	sel_WoHoB :  STD_LOGIC_VECTOR(1 downto 0);
signal	shiftLeft2toALU :  STD_LOGIC_VECTOR(31 downto 0);
signal	shiftLeftPC_to_MuxALUOutPC :  STD_LOGIC_VECTOR(31 downto 0);
signal	StoreToMem :  STD_LOGIC_VECTOR(31 downto 0);
signal	valor0_RegA :  STD_LOGIC_VECTOR(4 downto 0);
signal	valor227WriteData :  STD_LOGIC_VECTOR(31 downto 0);
signal	valor253 :  STD_LOGIC_VECTOR(31 downto 0);
signal	valor254 :  STD_LOGIC_VECTOR(31 downto 0);
signal	valor4 :  STD_LOGIC_VECTOR(31 downto 0);
signal	valorExtend16_32 :  STD_LOGIC_VECTOR(31 downto 0);
signal	valorRegA :  STD_LOGIC_VECTOR(31 downto 0);
signal	valorRegB :  STD_LOGIC_VECTOR(31 downto 0);
signal	vectorDaALUOut :  STD_LOGIC_VECTOR(31 downto 0);
signal	vectorDaMem :  STD_LOGIC_VECTOR(31 downto 0);
signal	vectorPC :  STD_LOGIC_VECTOR(31 downto 0);


BEGIN 



b2v_ALU : ula32
PORT MAP(A => saida_Mux_RegAtoUla32,
		 B => saida_Mux_RegBUla32,
		 Seletor => sel_ALUop,
		 Overflow => sel_overflowALU,
		 z => flagZeroALU,
		 Menor => flagSLTALU,
		 S => saidaALU);

b2v_ALUOut : registrador
PORT MAP(Clk => sel_clk,
		 Reset => sel_reset,
		 Load => sel_ALUOutWrite,
		 Entrada => saidaMux_sltToALUOut,
		 Saida => vectorDaALUOut);

b2v_Banco_Reg : banco_reg
PORT MAP(Clk => sel_clk,
		 Reset => sel_reset,
		 RegWrite => sel_RegWrite,
		 ReadReg1 => instrucao(25 downto 21),
		 ReadReg2 => instrucao(20 downto 16),
		 WriteData => entradaWriteData,
		 WriteReg => entradaWriteReg,
		 ReadData1 => entradaRegA,
		 ReadData2 => entradaRegB);

b2v_cause : registrador
PORT MAP(Clk => sel_clk,
		 Reset => sel_reset,
		 Load => sel_causeWrite,
		 Entrada => entradaCauseException,
		 Saida => causeException);

b2v_EPC : registrador
PORT MAP(Clk => sel_clk,
		 Reset => sel_reset,
		 Load => sel_EPCWrite,
		 Entrada => saidaALU,
		 Saida => saidaEPC);

b2v_extensor1_32 : extensor1_32
PORT MAP(entrada => flagSLTALU,
		 saida => resulSLTALU);

b2v_extensor_IR_ALU : mux2
PORT MAP(seletor => sel_usaSinal,
		 entrada0 => extendSemSinal16_32,
		 entrada1 => extendComSinal16_32,
		 saida => valorExtend16_32);

b2v_extensorSemSinal : extensorsemsinal
PORT MAP(entrada => instrucao(15 downto 0),
		 saida => extendSemSinal16_32);

b2v_extensorSinal : extensorsinal
PORT MAP(entrada => instrucao(15 downto 0),
		 saida => extendComSinal16_32);

andPCWriteCond <= sel_PCwriteCond AND saida_MUX_BEQorNE;

loadPC <= andPCWriteCond OR sel_PCwrite;

notFlagZeroALU <= NOT(flagZeroALU);


b2v_IR : instr_reg
PORT MAP(Clk => sel_clk,
		 Reset => sel_reset,
		 Load_ir => sel_IRwrite,
		 Entrada => vectorDaMem,
		 Instr15_0 => instrucao(15 downto 0),
		 Instr20_16 => instrucao(20 downto 16),
		 Instr25_21 => instrucao(25 downto 21),
		 Instr31_26 => instrucao(31 downto 26));

b2v_Loads : loads
PORT MAP(entrada => MDRtoLoads,
		 seletor => sel_WoHoB,
		 saida => MDRtoWriteData);

b2v_LuiBox : luibox
PORT MAP(entrada => instrucao(15 downto 0),
		 saida => LuitoWriteData);

b2v_MDR : registrador
PORT MAP(Clk => sel_clk,
		 Reset => sel_reset,
		 Load => sel_RegMDR,
		 Entrada => vectorDaMem,
		 Saida => MDRtoLoads);

b2v_Memoria : memoria
PORT MAP(Clock => sel_clk,
		 Wr => sel_MemWrite,
		 Address => AdressMem,
		 Datain => StoreToMem,
		 Dataout => vectorDaMem);

b2v_multiplicador : multiplicador
PORT MAP(multControl => sel_MultControl,
		 clk => sel_clk,
		 reset => sel_reset,
		 multiplicador => valorRegB,
		 multiplicando => valorRegA,
		 finishMultControl => sel_finishMultControl,
		 saidaHI => multHI,
		 saidaLO => multLO);

b2v_mux_cause : mux2
PORT MAP(seletor => causeException(0),
		 entrada0 => valor254,
		 entrada1 => valor253,
		 saida => Mux_causeToMuxALUOutPC);

b2v_Mux_count_RegA : mux2_5
PORT MAP(seletor => sel_countControl,
		 entrada0 => instrucao(10 downto 6),
		 entrada1 => valor0_RegA,
		 saida => countToRegA);

b2v_mux_entradaPC : mux2
PORT MAP(seletor => excecao_to_PC,
		 entrada0 => entradaPC,
		 entrada1 (7 downto 0) => MDRtoWriteData (7 downto 0),
		 entrada1 (31 downto 8) => "000000000000000000000000",
		 saida => saidaMuxEntradaPC);

b2v_mux_excecao : mux2
PORT MAP(seletor => sel_causeSrc,
		 entrada0 => causaExcecaoZero,
		 entrada1 => causaExcecaoUm,
		 saida => entradaCauseException);

b2v_Mux_IR_BancoReg : mux4_5bits
PORT MAP(entrada0 => instrucao(20 downto 16),
		 entrada1 => instrucao(15 downto 11),
		 entrada2 => Reg31,
		 entrada3 => Reg29,
		 seletor => sel_RegDst,
		 saida => entradaWriteReg);

b2v_Mux_IR_WriteData : mux8
PORT MAP(entrada0 => vectorDaALUOut,
		 entrada1 => MDRtoWriteData,
		 entrada2 => saidaHILO,
		 entrada3 => LuitoWriteData,
		 entrada4 => vectorPC,
		 entrada5 => valor227WriteData,
		 entrada6 => entradaNula,
		 entrada7 => entradaZero,
		 seletor => sel_DataToReg,
		 saida => entradaWriteData);

b2v_Mux_PC_Mem : mux2
PORT MAP(seletor => sel_IorD,
		 entrada0 => vectorPC,
		 entrada1 => vectorDaALUOut,
		 saida => AdressMem);

b2v_Mux_RegAtoALU : mux3
PORT MAP(entrada0 => vectorPC,
		 entrada1 => valorRegA,
		 entrada2 => saidaEPC,
		 seletor => sel_ALUSrcA,
		 saida => saida_Mux_RegAtoUla32);

b2v_Mux_slt : mux2
PORT MAP(seletor => LTControl,
		 entrada0 => resulSLTALU,
		 entrada1 => saidaALU,
		 saida => saidaMux_sltToALUOut);

b2v_MuxALUoutPC : mux4
PORT MAP(entrada0 => saidaALU,
		 entrada1 => vectorDaALUOut,
		 entrada2 => shiftLeftPC_to_MuxALUOutPC,
		 entrada3 => Mux_causeToMuxALUOutPC,
		 seletor => sel_PCSorce,
		 saida => entradaPC);

b2v_MuxBEQorBNE : mux1b
PORT MAP(entrada0 => flagZeroALU,
		 entrada1 => notFlagZeroALU,
		 seletor => sel_BEQorBNE,
		 saida => saida_MUX_BEQorNE);

b2v_MuxHiLo : mux2
PORT MAP(seletor => sel_HILO,
		 entrada0 => multHI,
		 entrada1 => multLO,
		 saida => saidaHILO);

b2v_PC : registrador
PORT MAP(Clk => sel_clk,
		 Reset => sel_reset,
		 Load => loadPC,
		 Entrada => saidaMuxEntradaPC,
		 Saida => vectorPC);

b2v_RegADesloc : shifterregister
PORT MAP(Clk => sel_clk,
		 Reset => sel_reset,
		 Entrada => entradaRegA,
		 N => countToRegA,
		 Shift => sel_RegAControl,
		 Saida => valorRegA);

b2v_RegB : registrador
PORT MAP(Clk => sel_clk,
		 Reset => sel_reset,
		 Load => sel_RegBWrite,
		 Entrada => entradaRegB,
		 Saida => valorRegB);

b2v_RegB_ALU : mux4
PORT MAP(entrada0 => valorRegB,
		 entrada1 => valor4,
		 entrada2 => valorExtend16_32,
		 entrada3 => shiftLeft2toALU,
		 seletor => sel_ALUSrcB,
		 saida => saida_Mux_RegBUla32);

b2v_shiftLeft2 : shiftleft2
PORT MAP(entrada => extendComSinal16_32,
		 saida => shiftLeft2toALU);

b2v_shiftLeft2_26 : shiftleft2_26b
PORT MAP(entrada0 => instrucao(25 downto 0),
		 entrada1 => vectorPC(31 downto 28),
		 saida => shiftLeftPC_to_MuxALUOutPC);

b2v_store : masksave
PORT MAP(entradaMem => vectorDaMem,
		 entradaReg => valorRegB,
		 seletor => sel_WoHoB,
		 saida => StoreToMem);
overflowALU <= sel_overflowALU;
sel_clk <= clk;
sel_reset <= reset;
sel_PCwriteCond <= PCWriteCond;
sel_BEQorBNE <= BEQorBNE;
sel_PCwrite <= PCWrite;
sel_ALUOutWrite <= ALUOutWrite;
sel_IRwrite <= IRWrite;
sel_MemWrite <= MemWrite;
sel_IorD <= IorD;
sel_RegBWrite <= RegBWrite;
sel_RegWrite <= RegWrite;
sel_RegMDR <= RegMDR;
sel_WoHoB <= WoHoB;
sel_HILO <= HILO;
sel_MultControl <= MultControl;
sel_countControl <= countControl;
sel_RegAControl <= RegAControl;
sel_DataToReg <= DataToReg;
sel_RegDst <= RegDst;
sel_causeWrite <= causeWrite;
sel_causeSrc <= causeSrc;
sel_PCSorce <= PCSource;
sel_EPCWrite <= EPCWrite;
sel_ALUSrcA <= AluSrcA;
sel_usaSinal <= usaSinal;
sel_ALUSrcB <= AluSrcB;
sel_ALUop <= AluOp;
FinishMultControl <= sel_finishMultControl;
funct(5 downto 0) <= instrucao(5 downto 0);
opcode(5 downto 0) <= instrucao(31 downto 26);

causaExcecaoUm <= "00000000000000000000000000000001";
causaExcecaoZero <= "00000000000000000000000000000000";
entradaNula <= "00000000000000000000000000000000";
entradaZero <= "00000000000000000000000000000000";
Reg29 <= "11101";
Reg31 <= "11111";
valor0_RegA <= "00000";
valor227WriteData <= "00000000000000000000000011100011";
valor253 <= "00000000000000000000000011111101";
valor254 <= "00000000000000000000000011111110";
valor4 <= "00000000000000000000000000000100";
END; 